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9-channel, 14-bit current dac with spi interface max5113 evaluation kit available 19-6401; rev 2; 5/13 general description the max5113 is a 14-bit, 9-channel, current-output digital-to-analog converter (dac). the device operates from a low +3.0v power supply and provides 14-bit per - formance without any adjustment. the device?s output ranges are optimized to bias a high- power tunable laser source. each of the 9 channels pro - vides a current source. channels 1 and 2 provide 10ma current. an internal multiplexer switches the outputs of each channel to one of four external nodes. channel 3 pro - vides a selectable current of 2ma or 20ma. channel 4 pro - vides 90ma. channel 5 provides 180ma. channel 6 pro - vides a selectable current of -60ma or +300ma. channel 7 provides 90ma. channels 8 and 9 provide a selectable current of 15ma or 35ma. connect dac outputs in parallel to obtain additional current or to achieve higher resolution. the device contains an internal reference. an spi interface drives the device with clock rates of up to 25mhz. an active-high asynchronous clr input resets dac codes to zero independent of the serial interface. the device provides a separate power-supply input for driving the interface logic. the max5113 is specified over the -40 n c to +105 n c temperature range, and is available in 3mm x 3mm, 36-bump wlp and 5mm x 5mm, 32-pin tqfn packages. features s low 3.0v supply s integrated multiplexers for outputs 1 and 2 s increased current or resolution with outputs connected in parallel s spi-compatible serial interface s internal reference s overtemperature protection s operates over the -40 n c to +105 n c temperature range s available in 36-bump wlp or 32-pin tqfn packages applications tunable laser diode biasing ordering information note: all devices are specified over the -40c to +105c operating temperature range.+ denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. typical operating circuit part interface pin-package max5113gwx+t spi 36 wlp max5113gtj+ spi 32 tqfn-ep* max5113 1 din 2 sclk 3 cs 4 dout 5 v ddi 6 dgnd 7 agnd 8 clr 9 op7 10 v dd1 11 op8 12 op3 13 n.c. 14 op4 15 v dd2 16 op1a 24 v ss 23 v dd5 22 op6 21 v dd4 20 v dd3 19 op1d 18 op1c 17 op1b 32 v dd7 31 op5 30 op9 29 v dd6 28 op2a 27 op2b 26 op2c 25 op2d c2 0.1 f c1 0.1 f c9 0.1 f c8 0.1 f c7 0.1 f c4 0.1 f c6 0.1 f c5 0.1 f c c100.1 f digital power supply v dd v dd v dd v dd v ss c3 0.1 f v dd for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maximintegrated.com. downloaded from: http:///
2 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd ................. ??????????..-0.3v to +4.0v v ss to agnd ........................................................ -6.0v to +0.3v v ddi to agnd ...................................................... -0.3v to +6.0v op6 to agn.....the higher of (v dd - 9v), (v ss - 0.3v) and -6.0v to the lower of (v dd + 0.3v) and +4.0v op1 to op5 and op7, op8, op9 to agnd ... -0.3v to the lower of (v dd + 0.3v) and +4.0v dout to dgnd ................. -0.3v to the lower of (v ddio + 0.3v) and +6.0v n.c. to agnd ...... -0.3v to the lower of (v dd + 0.3v) and +4.0v digital i/os to dgnd ............................................ -0.3v to +6.0v agnd to dgnd ................................................... -0.3v to +0.3v all other pins to agnd. .. ??????????.-0.3v to +4.0v continuous power dissipation ( t a = +70 n c) wlp (derate at 26.3mw/ n c above +70 n c) .................. 2104mw tqfn (derate at 34.5mw/ n c above +70 n c) .............. 2758mw maximum current into any pin ........................................ 380ma operating temperature range ........................ -40 n c to +105 n c storage temperature range ............................ -65 n c to +150 n c junction temperature ..................................................... +150 n c lead temperature (tqfn only, soldering, 10s) ............. +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v dd = +2.6v to +3.3v, v ss = -4.75v to -5.46v, v ddi = +1.8v to +5.25v, agnd = dgnd, t a = -40 n c to +105 n c, v op1? v op5 = v op6 sourcing = v op7, v op8, and v op9 = v dd - 1v, v op6 sinking = v ss + 1v, unless otherwise noted. typical specifications are at v dd = +3.0v, v ss = -5.2v, t a = +25 n c. specifications apply to all dacs and outputs, unless otherwise noted.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 1) tqfn junction-to-ambient thermal resistance ( q ja ) .......... 29 n c/w junction-to-case thermal resistance ( q jc ) .............. 1.7 n c/w wlp junction-to-ambient thermal resistance ( q ja ) .......... 38 n c/w parameter symbol conditions min typ max units static performance resolution n 14 bits differential nonlinearity dnl guaranteed monotonic q 0.5 q 1.0 lsb integral nonlinearity inl op1?op6 source and op9 q 2 q 8 lsb op6 sink q 8 ideal gain i gain i max /2 14 ma/lsb gain error (note 3) ge all but op3, 2ma and op6 sink q 1.3 %fs op3, 2ma q 1.5 op6 sink q 5 gain error tempco (note 4) getc all but op6 sink q 50 ppm/ n c op6 sink q 15 full-scale output i max op1 and op2 10 ma op3 2ma fs range 2 20ma fs range 20 op4 90 op5 180 op6 current source 300 op6 current sink -60 op7 90 op8 and op9 15ma fs range 15 35ma fs range 35 downloaded from: http:///
3 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 electrical characteristics (continued) (v dd = +2.6v to +3.3v, v ss = -4.75v to -5.46v, v ddi = +1.8v to +5.25v, agnd = dgnd, t a = -40 n c to +105 n c, v op1? v op5 = v op6 sourcing = v op7, v op8, and v op9 = v dd - 1v, v op6 sinking = v ss + 1v, unless otherwise noted. typical specifications are at v dd = +3.0v, v ss = -5.2v, t a = +25 n c. specifications apply to all dacs and outputs, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units offset error (note 3) oe op1 and op2 -120 -60 0 f a op3 2ma fs range -24 -12 0 20ma fs range -240 -120 0 op4 -1080 -540 0 op5 -2160 -1080 0 op6 current source -3600 -1800 0 op6 current sink 0 +360 +720 op7 -1080 -540 0 op8 and op9 15ma fs range -180 -90 0 35ma fs range -420 -210 0 offset error tempco (note 4) oetc op1 and op2 250 na/ n c op3 2ma fs range 50 20ma fs range 500 op4 2250 op5 4500 op6 current source 7500 op6 current sink 1500 op7 2250 op8 and op9 15ma fs range 375 35ma fs range 875 output compliance range v or all but op6 sink v gnd v dd - 1 v op6 sink v ss + 1 v dd dynamic performanceoutput resistance r out op1 and op2 2 m i op3 2ma fs range 10 20ma fs range 1 op4 0.2 op5 0.1 op6 current source 0.06 op6 current sink 0.04 op7 0.2 op8 and op9 15ma fs range 1.3 35ma fs range 0.56 current-output slew rate sr op1 and op2 5 ma/ f s op3 2ma fs range 1 20ma fs range 10 op4 45 op5 90 op6 current source 150 op6 current sink 30 op7 45 op8 and op9 15ma fs range 7.5 35ma fs range 17.5 downloaded from: http:///
4 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 electrical characteristics (continued) (v dd = +2.6v to +3.3v, v ss = -4.75v to -5.46v, v ddi = +1.8v to +5.25v, agnd = dgnd, t a = -40 n c to +105 n c, v op1? v op5 = v op6 sourcing = v op7, v op8, and v op9 = v dd - 1v, v op6 sinking = v ss + 1v, unless otherwise noted. typical specifications are at v dd = +3.0v, v ss = -5.2v, t a = +25 n c. specifications apply to all dacs and outputs, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units output settling time t os t o q 0.1% 15 f s noise at full scale (10khz) ino op1 and op2 1.6 na/ hz op3 2ma fs range 0.4 20ma fs range 3.4 op4 16 op5 31 op6 current source 56 op6 current sink 11 op7 16 op8 and op9 15ma fs range 2.8 35ma fs range 6.5 dac glitch impulsemajor-carry transition ioge op1 and op2 60 pc op3, 20ma 120 op4 540 op5 1080 op6 current source 1800 op6 current sink 360 op7 540 op8 and op9 15ma fs range 90 35ma fs range 210 dac output gnd switch resistance r gsw at 0.7v 50 i dac output gnd switch current i gsw at 0.7v 14 ma overtemperature detectorsovertemperature disable threshold t ovtd +160 n c overtemperature warning threshold t ovtw +150 n c power requirementspower-supply range v dd 2.6 3.3 v interface power-supply range v ddi 1.8 5.25 v negative supply range v ss -5.46 -5.2 -4.75 v supply current i dd no load, no i/o 500 600 f a negative supply current i ss -20 -11 f a power-on reset (por)por threshold v por 1.6 v por threshold hysteresis v porh 0.025 v downloaded from: http:///
5 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 electrical characteristics (continued) (v dd = +2.6v to +3.3v, v ss = -4.75v to -5.46v, v ddi = +1.8v to +5.25v, agnd = dgnd, t a = -40 n c to +105 n c, v op1? v op5 = v op6 sourcing = v op7, v op8, and v op9 = v dd - 1v, v op6 sinking = v ss + 1v, unless otherwise noted. typical specifications are at v dd = +3.0v, v ss = -5.2v, t a = +25 n c. specifications apply to all dacs and outputs, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units digital input characteristics (din, sclk, cs , clr) input low voltage v il v ddi = 2.2v to 5.25v 0.3 x v ddi v v ddi = 1.8v to 2.2v 0.2 x v ddi v input high voltage v ih v ddi = 2.2v to 5.25v 0.7 x v ddi v v ddi = 1.8v to 2.2v 0.8 x v ddi v input hysteresis v hys 250 mv input capacitance c in 10 pf input leakage current i in input = 0v or v ddi q 10 f a digital output characteristics (dout)output low voltage v ol v ddi = 2.2v to 5.5v, i sink = 5ma 0.40 v v ddi = 1.8v to 2.2v, i sink = 2ma 0.25 output high voltage v oh v ddi = 2.2v to 5.5v, i source = 5ma v ddi - 0.5 v v ddi = 1.8v to 2.2v, i source = 2ma v ddi - 0.3 v output three-state leakage i oz bhen = 0 q 0.01 q 1 f a output bus hold sinking current i bhk dout low, bhen = 1 -12 f a output bus hold sourcing current i bhc dout high, bhen = 1 +5 f a output three-state capacitance c oz 11 pf output short-circuit current i oss v ddi = 5.25v q 100 ma timing characteristics (note 5)serial clock frequency f sclk 0 25 mhz sclk period t cp v ddi = 1.8v to 5.25v 40 ns sclk pulse width low t cl v ddi = 1.8v to 5.25v, 60% duty cycle 16 ns sclk pulse width high t ch v ddi = 1.8v to 5.25v, 40% duty cycle 16 ns cs fall to sclk fall setup time t css0 to first sclk falling edge 16 ns cs fall to sclk fall hold time t csh0 applies to inactive fe preceding first fe 0 ns cs rise to sclk fall hold time t csh1 applies to 24th fe 0 ns din-to-sclk fall setup time t ds 8 ns din-to-sclk fall hold time t dh 8 ns sclk fall to dout settling time t dot v ddi = 2.2v to 5.5v, c load = 20pf 30 ns v ddi = 1.8v to 2.2v, c load = 20pf 60 sclk fall to dout hold time t doh c load = 0pf 2 ns sclk fall to dout disable t doz 24th active fe deassertion 2 30 ns downloaded from: http:///
6 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 note 2: specifications are 100% production tested at t a +25 n c. specifications for t a < +25 n c are guaranteed by design and characterization. note 3: configuration register write operation required following power-up for output offset adjustment. see the dac outputs sec- tion in the detailed description . all gain and offset errors include the effect of the internal reference and are guaranteed over temperature. gain error = (measured gain - i gain )/i gain . measured gain = (code 16383 dac output - code 500 dac output)/15883. offset error = code 500 dac output - (500 x measured gain). the device is trimmed such that offset error is negative, ensuring linear operation down to zero current output. note 4: guaranteed by design and characterization. not production tested. all gain and offset temperature coefficients include the effect of the internal reference. temperature coefficients are calculated by the ?box? method. for additional informa - tion, refer to maxim application note 4300: calculating the error budget in precision digital-to-analog converter (dac) applications . note 5: timing characteristics are tested and guaranteed with digital input conditions v ih = v ddi and v il = 0v. note 6: minimum pulse width required to realize functionally useful dac transitions. not production tested. see shutter mode settling time down and shutter mode settling time up graphs in the typical operating characteristics section. electrical characteristics (continued) (v dd = +2.6v to +3.3v, v ss = -4.75v to -5.46v, v ddi = +1.8v to +5.25v, agnd = dgnd, t a = -40 n c to +105 n c, v op1? v op5 = v op6 sourcing = v op7, v op8, and v op9 = v dd - 1v, v op6 sinking = v ss + 1v, unless otherwise noted. typical specifications are at v dd = +3.0v, v ss = -5.2v, t a = +25 n c. specifications apply to all dacs and outputs, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units cs fall to dout enable t doe v ddi = 2.2v to 5.5v, asynchronous 1 30 ns v ddi = 1.8v to 2.2v, asynchronous 1 40 cs rise to dout disable t csdoz stand alone, aborted sequence 35 ns cs rise to sclk fall t csa applies to 24th fe, aborted sequence 20 ns cs pulse-width high t cspw stand alone 20 ns sclk fall to cs fall t csf applies to 24th active fe 100 ns clr fall to cs fall t clrcs applies to dacs in reset mode only 20 ns clr pulse-width high t clrpw no dac is in shutter or gate mode 40 ns any dac is in shutter or gate mode (note 6) 500 downloaded from: http:///
7 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) gain error vs. analog supply voltage max5113 toc07 supply voltage (v) gain error (%fs) 3.2 3.1 2.7 2.8 2.9 3.0 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 -0.2 2.6 3.3 op6 sourceop5 op7 op6 sink op9, 35ma op2 op9op1 op8 op4 op3, 20ma op3, 2ma v ddi = v dd v ss = -5.2v op8, 35ma negative analog supply current vs. negative supply voltage max5113 toc06 supply voltage (v) supply current (a) -4.7 -4.9 -5.1 -5.3 11.58 11.60 11.62 11.64 11.66 11.6811.56 -5.5 -4.5 positive analog supply current vs. analog supply voltage max5113 toc05 supply voltage (v) supply current (ma) 3.2 3.1 2.7 2.8 2.9 3.0 0.505 0.510 0.515 0.520 0.525 0.530 0.535 0.5400.500 2.6 3.3 v ddi = v dd v ss = -5.2v all dacs off digital supply current vs. digital supply voltage max5113 toc04 digital input voltage (v) digital supply current (a) 5 4 3 2 1 0 200 400 600 800 1000 1200 1400 1600 1800 -200 0 v ddi = 5.25v inputincreasing input decreasing digital supply current vs. digital input voltage max5113 toc03 digital supply current (a) 50 100 200150 250 300 -50 0 digital input voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 v ddi = 3.0v inputincreasing input decreasing digital supply current vs. digital input voltage max5113 toc02 digital input voltage (v) digital supply current (a) 1.2 1.4 1.6 1.0 0.8 0.6 0.4 0.2 0 10 20 30 40 50 -10 0 1.8 v ddi = 1.8v inputincreasing input decreasing digital supply current vs. temperature max5113 toc01b temperature (c) digital supply current (a) 80 60 40 20 0 -20 0.35 0.40 0.45 0.50 0.55 0.600.30 -40 100 v ddi = 5.25v v ddi = 4.3v v ddi = 3.3v v ddi = 3v v ddi = 2.7v analog supply current vs. temperature max5113 toc01 temperature (c) supply current (ma) 80 60 20 40 0 -20 0.500 0.505 0.510 0.515 0.520 0.525 0.530 0.535 0.5400.495 -40 100 v ddi = 3v, all dacs off v dd = 3.3v v dd = 3v v dd = 2.6v downloaded from: http:///
8 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (continued) (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) op3, 20ma integral nonlinearity vs. digital input code max5113 toc14 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op3, 2ma integral nonlinearity vs. digital input code max5113 toc13 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op2 integral nonlinearity vs. digital input code max5113 toc12 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op1 integral nonlinearity vs. digital input code max5113 toc11 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 offset error change vs. temperature max5113 toc10 temperature (c) offset error change (%fs) 100 80 60 40 20 0 -20 -0.06 -0.02-0.04 0 0.02 0.060.04 0.08 -0.08 -40 v ddi = v dd v ss = -5.2v op2op6 op9 op1, op8 op7op3 op5 op6 sink op4 offset error change vs. analog supply voltage max5113 toc09 supply voltage (v) offset error change (%fs) 3.2 3.1 2.7 2.8 2.9 3.0 2.6 3.3 op3op2, op4 op6, op8, op9op5 op7 op1 v ddi = v dd v ss = -5.2v -0.03 -0.02 -0.01 0.01 0 0.02 0.03 -40 -20 02 04 0608 0 100 gain error vs. temperature temperature (c) max5113 toc08 gain error (%fs) -0.1 0.1 0.2 0.3 0.4 0.5 0.6 -0.2 0 v ss = -5.2v op6 sourceop5 op9, 35ma op6 sink op7op2 op9op1 op8 op4 op3, 20ma op3, 2ma op8, 35ma downloaded from: http:///
9 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (continued) (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) op5 integral nonlinearity vs. digital input code max5113 toc16 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op4 integral nonlinearity vs. digital input code max5113 toc15 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op9, 35ma integral nonlinearity vs. digital input code max5113 toc21b digital input code (decimal) inl (lsb) 12288 8192 4096 0 16384 -6 -4 -2 0 2 4 6 8 -8 op9, 15ma integral nonlinearity vs. digital input code max5113 toc21 digital input code (decimal) inl (lsb) 12288 8192 4096 0 16384 -6 -4 -2 0 2 4 6 8 -8 op8, 35ma integral nonlinearity vs. digital input code max5113 toc20b digital input code (decimal) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op8, 15ma integral nonlinearity vs. digital input code max5113 toc20 digital input code (decimal) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op7 integral nonlinearity vs. digital input code max5113 toc19 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op6 source integral nonlinearity vs. digital input code max5113 toc18 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 op6 sink integral nonlinearity vs. digital input code max5113 toc17 digital input code (lsb) inl (lsb) 12288 8192 4096 -6 -4 -2 0 2 4 6 8 -8 0 16384 downloaded from: http:///
10 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (continued) (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) op6 sink differential nonlinearity vs. digital input code max5113 toc30 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op5 differential nonlinearity vs. digital input code max5113 toc29 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op4 differential nonlinearity vs. digital input code max5113 toc28 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op3, 20ma differential nonlinearity vs. digital input code max5113 toc27 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op3, 2ma differential nonlinearity vs. digital input code max5113 toc26 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op2 differential nonlinearity vs. digital input code max5113 toc25 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op1 differential nonlinearity vs. digital input code max5113 toc24 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 integral nonlinearity vs. temperature max5113 toc23 temperature (c) inl (lsb) 80 60 20 40 0 -20 -7 -5 -3 -1 1 3 5 7 9 -9 -40 100 integral nonlinearity vs. analog supply voltage max5113 toc22 supply voltage (v) inl (lsb) 3.2 3.1 2.9 3.0 2.8 2.7 -7 -5 -3 -1 1 3 5 7 9 -9 2.6 3.3 downloaded from: http:///
11 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (continued) (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) op7 differential nonlinearity vs. digital input code max5113 toc32 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op6 source differential nonlinearity vs. digital input code max5113 toc31 digital input code (lsb) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 high-to-low major code transition output transient max5113 toc36 14.6 lsb/div 2s/div delayed trigger op7, 90ma fs code 16256 to 16255 low-to-high major code transition output transient max5113 toc35 14.6 lsb/div 2s/div delayed trigger op7, 90ma fs code 16255 to 16256 op8, 15ma differential nonlinearity vs. digital input code max5113 toc34 digital input code (decimal) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op9, 35ma differential nonlinearity vs. digital input code max5113 toc34b digital input code (decimal) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op8, 35ma differential nonlinearity vs. digital input code max5113 toc33b digital input code (decimal) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 op8, 15ma differential nonlinearity vs. digital input code max5113 toc33 digital input code (decimal) dnl (lsb) 12288 8192 4096 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 16384 downloaded from: http:///
12 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (continued) (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) multicode transition transient op8 code 9690 to 9630 (t/h on) max5113 toc36c 23 lsb/div 2s/div output6 high to low code 0.1% settling time max5113 toc37b 2s/div op6, 255ma to 75ma sclk, 0 to 3v op6 output error 0.2ma/div sclk falling edge 2v/div 4s/div d t = 10s 0.1% d i = 0.225ma shutter mode settling time up max5113 toc39 op6 50ma/div 0a 1s/div multicode transition transient op8 code 9690 to 9630 (t/h off) max5113 toc36b 23 lsb/div 2s/div output 6 low to high code 0.1% settling time max5113 toc37 2s/div op6, 75ma to 225ma sclk, 0 to 3v op6 output error 0.2ma/div sclk falling edge 2v/div 4s/div d t = 12s 0.1% d i = 0.225ma shutter mode settling time down max5113 toc38 op6 50ma/div 0a 4s/div downloaded from: http:///
13 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 typical operating characteristics (continued) (v dd = 3.0v, t a = +25 n c, unless otherwise noted.) interface feedthrough max5113 toc41 op3, 20ma code = 10000 4.1 lsb/div din, sclk 2v/div 40ns/div channel-to-channel analog crosstalk max5113 toc40 op2a code = 10000 4.9 lsb/div op5 code = 164 to 16383 100ma/div 4s/div command sequence feedthrough max5113 toc42 op7, 90ma fs code = 10000 5.5 lsb/div din sclk 4s/div downloaded from: http:///
14 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 pin configurations pin description top view (bump side down) ab cd wlp ef 2 4 1 5 6 3 + + din sclk v ddi dgnd clr op7 op5 v dd7 dout i.c. v dd1 op8 op9 v dd6 cs agnd v dd9 op3 op2a v dd10 op2b n.c. v dd8 op4 op2c v dd5 v dd4 v dd3 v dd2 op1a v ss op2d op6 op1d op1c op1b max5113 max5113 tqfn top view 2930 28 27 1211 13 sclk dout v ddi dgnd agnd 14 din v dd5 v dd4 v dd3 v ss op1dop1c 1 2 op2a 4 5 6 7 23 24 22 20 19 18 v dd6 op9 op4 n.c. op3op8 cs op6 3 21 31 10 op5 v dd1 32 9 v dd7 ep op7 op2b 26 15 v dd2 op2c 25 16 op1a clr op1b 8 17 op2d pin name function wlp tqfn-ep a1 1 din spi data in b1 31 op5 dac 5 output, 180ma full scale c1 30 op9 dac 9 output, 15ma or 35ma full scale d1 28 op2a dac 2 multiplexer output a, 10ma full scale e1 26 op2c dac 2 multiplexer output c, 10ma full scale f1 24 v ss negative power supply a2 2 sclk spi clock input b2 32 v dd7 dac 5 output positive power supply. internally connected to v dd6 and v dd10. c2 29 v dd6 dac 5 output positive power supply (wlp). internally connected to v dd7 and v dd10. dac 5 output and dac 2 output positive power supply (tqfn). internally connected to v dd7 and v dd10. d2 ? v dd10 dac 2 output and dac 9 output positive power supply. internally connected to v dd6 and v dd7. e2 23 v dd5 dac 6 output positive power supply. internally connected to v dd3 and v dd4 . f2 25 op2d dac 2 multiplexer output d, 10ma full scale downloaded from: http:///
15 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 pin description (continued) pin name function wlp tqfn-ep a3 5 v ddi interface power supply. connect to v dd or to a separate supply to allow for a different interface voltage. b3 4 dout spi data out c3 3 cs active-low spi chip select d3 27 op2b dac 2 multiplexer output b, 10ma full scale e3 21 v dd4 dac 6 output positive power supply. internally connected to v dd5 and v dd3 . f3 22 op6 dac 6 output, -60ma or 300ma full scale a4 6 dgnd digital ground b4 ? i.c. internally connected. connect to dgnd. c4 7 agnd analog ground d4 13 n.c. no internal connection. must obey absolute maximum ratings . e4 20 v dd3 dac6 output positive power supply. internally connected to v dd5 and v dd4 . f4 19 op1d dac 1 multiplexer output d, 10ma full scale a5 8 clr active-high clear b5 10 v dd1 dac 7 output positive power supply (wlp)dac 3 output and dac 7 output and dac8 output positive power supply (tqfn) c5 ? v dd9 dac 3 output and dac 8 output positive power supply d5 ? v dd8 dac 4 output positive power supply e5 15 v dd2 dac 1 output positive power supply (wlp)dac 1 output and dac 4 output positive power supply (tqfn) f5 18 op1c dac 1 multiplexer output c, 10ma full scale a6 9 op7 dac 7 output, 90ma full scale b6 11 op8 dac 8 output, 15ma or 35ma full scale c6 12 op3 dac 3 output, 2ma or 20ma full scale d6 14 op4 dac 4 output, 90ma full scale e6 16 op1a dac 1 multiplexer output a, 10ma full scale f6 17 op1b dac 1 multiplexer output b, 10ma full scale ? ? ep exposed pad (tqfn only). internally connected to agnd. connect to a ground plane to enhance thermal dissipation. downloaded from: http:///
16 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 functional diagram 14-bit dac gnd cs sclk i.c. dout din clr v ddi v dd agnd dgnd v ss v ref control logic op4 14-bit dac 14-bit dac 14-bit dac 14-bit dac op1a op1b op1c op1d op2a op2b op2c op2d op3 op5 op6 op7 op8 op9 max5113 downloaded from: http:///
17 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 detailed description the max5113 output ranges are optimized to bias a high-power tunable laser source. see table 1 for the output current range available on each dac output. the dacs and highly stable internal reference are fac - tory trimmed to ensure the outputs are within the speci - fications. connect dacs in parallel to increase current drive or resolution. dac outputs the dac configuration registers (01h?09h) control the configuration of each dac. the individual configuration register for each channel must be written to after a power-up event, even if the default values are written. this ensures the device will meet guaranteed offset performance specifications. dacs 1 and 2 drive four 2:1 multiplexers. the multiplexers route each dac output to one of four outputs. configure unused outputs as high impedance or connect to agnd. dac 3 full-scale output is selectable between 2ma and 20ma. dac 6 provides 300ma full-scale output when selected as a current source. when selected as a current sink, the full 14 bits are available between 0 and -60ma. a typi - cal application for dac 6 is to drive an optical amplifier where a current source is varied to set the gain or where a current sink is varied to set the attenuation. all other dacs are positive current source dacs. dacs 8 and 9 full-scale outputs are selectable between 15ma and 35ma. the output range of dacs 3, 8 and 9 is selected using the rng bit in the individual configuration registers. the dac 6 polarity and full-scale output is set by the sw_pol bit in the dac 6 register. output track and hold all channels feature a track-and-hold circuit to improve glitch performance. in common with all dacs of this type, the max5113 dacs will glitch when in transi - tion from one code to another. the size of the glitch is defined by the size of the transition and where in the overall range the transition occurs. in general, a small transition results in a small glitch. however, this is not absolute. the track-and-hold circuit may be enabled to reduce the glitch size to close to zero. the track and hold can be enabled independently for each channel by set - ting bit 12 in the individual dac configuration registers (01h?09h).when enabled, the track and hold will engage after the 24th sclk in the spi frame, setting a new dac code. this will hold the output level until the dac section has settled. there is a small negative offset present in the output level while the track and hold is engaged. approximately 10 lsb. the track and hold is engaged for 6s, typical. it then disengages and the channel will transition to its new level with no glitch. dac ground switch all dacs include a programmable switch to connect the output to ground when the dac code is set to zero. the switch is open when the configuration bit is set to 0 and code zero is programmed. in this case, the output drivers are disabled, and the outputs set to high impedance. the dac switch configuration is set for each individual dac; see the 01h?09h: individual dac (1 to 9) configuration registers section. the global dac switch-override bits (gswg[1:0]) in the general configuration register (00h) override all switch selections when applied. clear function (clr) the clear function allows the access of modes of opera - tion through a single active-high input, clr. the behav - ior of each dac with clr asserted is independently configurable. see the clr interaction section. the clear function can also be asserted in software by setting the sw_clr bit in the software reset command register; see the 0fh: software reset command register section. the clear function for each dac is programmed through the clr_cfg[1:0] bits in the individual dac configuration registers (01h?09h) as shown in the following: ? 00 (ignore): the assertion of clr does not affect the dac. table 1. typical full-scale output currents output output-current range capability (ma) low range (default) high range op1 0 to 10 reserved op2 0 to 10 reserved op3 0 to 2 0 to 20 op4 0 to 90 reserved op5 0 to 180 reserved op6 -60 to 0 or 0 to 300 reserved op7 0 to 90 reserved op8 0 to 15 0 to 35 op9 0 to 15 0 to 35 downloaded from: http:///
18 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 ? 01 (shutter): shutter mode applies to op6 only. for all other dacs, shutter mode produces the same effect as ignore. for op6, the output polarity stays negative for as long as clr is asserted (level sensitive). the current sink level is defined by the dac 6 shutter mode code register (1bh). once clr releases, the dac output returns to the previously programmed value as set in the dac 6 source mode code register (16h). ? 10 (gate): the dac is held at code zero (with ground switches engaged if enabled) as long as clr is asserted (level sensitive). once clr releases, the dac output returns to the previously programmed value as set in the dac 1?9 code register (10h?1ah). ? 11 (reset): the dac is set to code zero (with ground switches engaged if enabled) when clr is asserted and remains at code zero after clr is released (edge sensitive). while the clear operation is in effect, dac channels configured in ignore, shutter, or gate mode continue to accept new code settings. dac channels configured in reset mode do not accept code changes until the clear operation is terminated. software clear interactions the device provides a software-accessible version of the clear function (sw_clr), which allows access to the clear functionality directly through the spi interface (see the 0fh: software reset command register sec - tion). when the command 0fh is used to launch a clear operation, the affected dac outputs are held in the clear position, determined by the clear configuration settings. this happens from the time when the 0fh com - mand requesting a clear operation is completed until a second 0fh command requesting removal of the clear operation is completed. the software- and pin-based clear operations are independently controlled and can be used individually or together without conflict. the devices provide an internal logic-or circuitry. power-on reset (por), power brownout the device contains a por circuit with a threshold of 1.6v (typ) and a hysteresis of 0.025v (typ). por ensures that the device resets all registers to default conditions as v dd rises through the upper por threshold. the default condition of all dac registers is code zero with ground switches engaged, ensuring that no large output current transients damage the load during initial power-up. in a v dd brownout situation, v dd must fall below the lower por threshold before a por is issued when v dd rises again. as v dd falls, the device eventually loses regulation. however, the device is designed to avoid any large output current transients that could damage the load. software reset and standby functions the device contains a software reset function. the soft - ware reset function resets all code and configuration registers to default conditions. write a 1 to the rst bit in the software reset command register (0fh) to initiate reset. the rst bit is not persistent, so writing a 0 to reset the bit is not required. the device includes a software standby function that causes all dac code registers (10h?1bh) to be set to code zero. write a 1 to the stdby bit in the software reset command register (0fh) to initiate the standby function. stdby bit is not persistent, so writing a 0 to reset the bit is not required. the software standby function is a subset of the software reset function. the software reset function takes effect when both functions are issues. overtemperature error handling the device features an on-chip temperature protection circuit to prevent the device from overheating when all dacs output the maximum programmed current. when the die temperature rises above the threshold tempera - ture, +160 n c, the pro_temp bit in the status/revision readback command register (0eh) is set and the device enters an overtemperature shutdown mode. all dacs are set to code zero, but the control interface remains active, thereby allowing the host processor to read back the device status. the pro_temp bit is latched and, therefore, the device can only be reset by a software reset command, a software standby command, or by cycling the power. the device features an overtemperature status bit, ovr_temp. the ovr_temp bit is not latched, and is set if the device temperature is above the protection threshold. the ovr_temp bit allows the host processor to determine if the device is too hot to reset. if a software reset is attempted while the device is above the protec - tion threshold, the command is ignored. similarly, above the threshold die temperature, the device immediately enters shutdown mode when power is cycled. the device features a warning bit, hi_temp. the warn - ing bit is not latched and serves as a high-temperature status indicator bit. the hi_temp bit is set when the die temperature is typically 10 n c below the overtemperature protection threshold. see the applications information section for more detail on calculating die temperature and heat-sinking requirements. downloaded from: http:///
19 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 table 2. user register/command summary user configuration registers table 2 shows a summary of the register map. register address (hex) access pairable register name 00h w y general configuration 01h w y dac 1 configuration 02h w y dac 2 configuration 03h w y dac 3 configuration 04h w y dac 4 configuration 05h w y dac 5 configuration 06h w y dac 6 configuration 07h w y dac 7 configuration 08h w y dac 8 configuration 09h w y dac 9 configuration 0ah ? ? reserved 0bh ? ? reserved 0ch ? ? reserved 0dh ? ? reserved 0eh r n status feedback and part id 0fh w y software reset/standby/clear 10h w y dac 1?9 code 11h w y dac 1 code 12h w y dac 2 code 13h w y dac 3 code 14h w y dac 4 code 15h w y dac 5 code 16h w y dac 6 source mode code 17h w y dac 7 code 18h w y dac 8 code 19h w y dac 9 code 1ah w y dac 6 sink mode code 1bh w y dac 6 shutter mode code 1ch ? ? reserved 1dh ? ? reserved 1eh ? ? reserved 1fh w y dac 6 polarity control downloaded from: http:///
20 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 register details 00h: general configuration register bit 15 14 13 12 11 10 9 8 name gswg[1:0] bhen x x x x x default 0 0 1 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name x x x x x x x x default 0 0 0 0 0 0 0 0 bit name description 15:14 gswg[1:0] global gsw configuration override00: individual dac gsw settings are unaltered 01: individual dac gsw settings are set to 0 (ground switches disabled) 10: individual dac gsw settings are set to 1 (ground switches enabled) 11: individual dac gsw settings are unaltered 13 bhen dout bus hold enable 0: bus hold circuit is disabled 1: bus hold circuit is enabled 12:0 x reserved downloaded from: http:///
21 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 01h?09h: individual dac (1 to 9) configuration registers note: any change to individual dac configuration settings resets the affected dac code to 0000h. bit 15 14 13 12 11 10 9 8 name gsw clr_cfg[1:0] t/h_en rng mux[3:1] default 1 0 0 0 1 0 1 0 bit 7 6 5 4 3 2 1 0 name mux0 x x x x x x x default 0 0 0 0 0 0 0 0 bit name description 15 gsw ground switch control0: output is left open when dac code = 0000h 1: output is connected to ground when dac code = 0000h. for dacs 1 and 2, this setting applies to the active mux output. 14:13 clr_cfg[1:0] clear configuration settings (determine how clr pin affects each dac)00 (ignore): the dac is not affected by the clr pin (default) 01 (shutter): dac output polarity is held negative (current level determined by 1bh) as long as the clr pin is asserted (level sensitive, applies to dac 6 only; otherwise, implements the ignore function) 10 (gate): dac output is held at zero scale (with ground switches engaged if enabled) as long as the clr pin is asserted (level sensitive) 11 (reset): dac output is set to zero scale (with ground switches engaged if enabled) when clr is asserted and remains valid after clr is removed (edge sensitive) 12 t/h_en track and hold enable0: track and hold disabled 1: track and hold enabled 11 rng range (dac 3, 8, and 9)0: dac full-scale output level is set to high range. 1: dac full-scale output level is set to low range. note: for all dacs not supporting rng settings, this bit is reserved and should be set to 1 (default). 10:7 mux[3:0] output mux settings for dac (mux settings are only supported for dac 1 and dac 2)0000: output a active, all others high impedance 0001: output b active, all others high impedance 0010: output c active, all others high impedance 0011: output d active, all others high impedance 01xx: all outputs high impedance (open) 1000: output a active, all others shunted to gnd 1001: output b active, all others shunted to gnd 1010: output c active, all others shunted to gnd 1011: output d active, all others shunted to gnd 11xx: all outputs shunted to gnd (default) 6:0 x reserved downloaded from: http:///
22 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 0eh: status/revision readback command register bit 15 14 13 12 11 10 9 8 name pro_temp ovr_temp hi_temp x part_id[3:0] default 0 0 0 0 0 0 0 1 bit 7 6 5 4 3 2 1 0 name rev_id[3:0] x x x x default 0 1 0 0 0 0 0 0 bit name description 15 pro_temp overtemperature protection indicator0: normal operation 1: device overtemperature protection engaged 14 ovr_temp overtemperature warning indicator0: normal operation 1: device temperature is too high (exceeding protection limit) 13 hi_temp high-temperature warning indicator0: normal operation 1: device temperature is high (nearing protection limit) 12 x reserved 11:8 part_id[3:0] part id code (0001) 7:4 rev_id[3:0] revision code (0100) 3:0 x reserved downloaded from: http:///
23 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 10h: group dac (1 to 9) code command register 0fh: software reset command register note: a software reset or standby command is required to exit overtemperature-protection mode once engaged (software clear does not qualify for an exit). bit 15 14 13 12 11 10 9 8 name rst stdby sw_clr x x x x x default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name x x x x x x x x default 0 0 0 0 0 0 0 0 bit name description 15 rst global reset (identical to a por)0: no operation 1: reset: all dac modes, configurations, and codes are returned to their default settings not persistent: the reset operation is contained within the command. it is not necessary to issue a second 0fh command to remove the reset condition. 14 stdby global standby (identical to a global power-down)0: no operation 1: standby: all dac codes are set to zero, but retain all configuration information not persistent: the standby operation is contained within the command. it is not necessary to issue a second 0fh command to remove the standby condition. exclusive: if rst and stdby are requested, stdby is not issued. 13 sw_clr software clear0: no operation/remove sw_clr 1: assert sw_clr persistent: the status of sw_clr remains in effect until changed by a later 0fh command. exclusive: if sw_clr and rst and/or stdby are requested, sw_clr is not issued. 12:0 x reserved bit 15 14 13 12 11 10 9 8 name b13 b12 b11 b10 b9 b8 b7 b6 default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name b5 b4 b3 b2 b1 b0 x x default 0 0 0 0 0 0 0 0 bit name description 15:2 b[13:0] group dac code setting in straight binary format. all dacs outputs update to code b[13:0] upon command completion. this command is primarily useful for speeding up testing and qualification. deglitching circuitry is not activated by group dac code operations. 1:0 x reserved downloaded from: http:///
24 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 11h?1bh: individual dac (1 to 9) code setting registers 1fh: dac 6 polarity command register dac 6 polarity operations software command 1fh (sw_pol) or the clr operation in shutter (01) mode controls the polarity of dac 6. dac 6 operates in a sink-current mode (0 to -60ma, determined by register 1ah in sink mode) when sw_pol is set high. when the software command is used, the requested polarity is held in effect from the time when the 1fh com - mand requesting a polarity change is completed until a second 1fh command requesting a polarity change operation is completed. when the shutter mode is used, dac 6 remains in shutter mode as long as clr is held high. the software- and clr-driven polarity operations are independently controlled and can be used indi - vidually or together without conflict. the device provides an internal logic-or operation. shutter allows the fast access to a programmable negative code, based on register 1bh, from either a source or sink mode with a controlled return to the original operating state upon release. gate mode is activated by asserting the clr or through the sw_clr bit. if gate mode is activated while the dac is set to sink mode, the dac remains in sink mode, but the cur - rent is reduced to 0ma for the duration of the gating event. note: 11h?19h are dac code settings for dacs 1?9, respectively. 1ah is the sink mode setting for dac 6. 1bh is the shutter mode setting for dac 6. see table 2. bit 15 14 13 12 11 10 9 8 name b13 b12 b11 b10 b9 b8 b7 b6 default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name b5 b4 b3 b2 b1 b0 x x default 0 0 0 0 0 0 0 0 bit name description 15:2 b[13:0] dac code settings in straight binary format3fffh = full-scale output 0000h = zero-scale output (gsw configuration settings apply) 1:0 x reserved bit 15 14 13 12 11 10 9 8 name sw_pol x x x x x x x default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name x x x x x x x x default 0 0 0 0 0 0 0 0 bit name description 15 sw_pol software polarity control (to dac 6 only)0: source-mode operation (0 to 300ma determined by 16h code, with gsw operation) 1: sink-mode operation (0 to -60ma determined by 1ah code, gsw operation disabled) 14:0 x reserved downloaded from: http:///
25 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 similarly, when reset mode is set, the dac remains in sink mode, but the current is reduced to 0ma and remains there during and after the reset event. all source-, sink-, and shutter-mode current settings are reset to zero by this operation. shutter mode is inaccessible while dac 6 is configured for reset. regardless of polarity/shutter setting, dac 6 continues to accept updated code settings for either source (16h), sink (1ah), or shutter mode (1bh) code registers, provid - ed the dac is not being held in any reset mode (through clr or sw_clr). spi interface the device features an spi interface capable of clock speeds up to 25mhz. figure 1 shows programming operation with 24 sclk periods, which is the minimum for a valid frame. for free-running sclk applications, t csh0 is shown with respect to the sclk falling edge preceding the first sclk falling edge (optional cycles shown in gray). to abort a command sequence, the rise of cs must pre - cede the 24th falling edge of sclk by t csa . table 3 shows how the contents of the user-command data are mapped into the command registry. the device requires a 1-byte command, also referred to as a regis - ter address, r[6:0] paired with a r/ w bit, followed by a 2-byte data word, d[15:0]. set r/ w to 0 for a write. set r/ w to 1 for a read. a full 24-bit spi command sequence is required for all spi command operations, regardless of the number of data bits actually used for the command. any commands terminating with less than a full 24-bit sequence are aborted without affecting the operation of the device, subject to t csa timing requirements. when a command sequence with more than 24 bits is provided, the command is executed on the 24th sclk falling edge and the remainder of the command is ignored. in addi - tion, the spi interface elements are disabled to reduce transient current consumption. all spi commands cause the device to assume control of the dout line from the first sclk edge through the 24th sclk edge. write-mode commands read out all zeros. after relinquishing the dout line, the device returns to a high-impedance mode. an optional bus hold circuit can be engaged to prevent leaving the dout line unbiased while not interfering with other devices on the bus. this is bit 13 in the general configuration register (00h). figure 1. minimum spi programming operationtable 3. spi user commands and data mapping with clock falling edges (24-bit frame) t csh1 t csf 1 2 3 4 5 6 7 8 23 r5 r6 r4 r3 r2 r1 r0 r/w din 1 din 0 t ch t cl t cp t dh t ds t css0 cs sclk din t csh0 24 1 r6' t csa t cspw t clrcs clr t clrpw d o 2 t doz t doh t dot t doe high ipedance high ipedance dot d o 15 10 din 15 din 14 edge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 din r6 r5 r4 r3 r2 r1 r0 r/ w d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout 0 0 0 0 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 0 high-z downloaded from: http:///
26 maxim integrated 9-channel, 14-bit current dac with spi interface max5113 clr interaction the device?s clear function allows the access of opera - tion modes through a single input, clr. each dac mode can be configured independently. the clr input interacts with dac code settings only. the clr input does not interfere with configurations or readback oper - ations. on-going spi transfers continue uninterrupted when clr is driven high. the effect of clr being driven depends on the clear configurations of the individual dac channel. code changes to any dac channels configured in ignore (00), shutter (01), or gate (10) mode are recog - nized, regardless of the status of clr. in shutter or gate mode, the dacs remain in the shutter or off positions for the duration of the clr assertion. once clr is released, the dacs return to the most recently programmed output values. any dac channels configured in reset (11) mode ignore code changes contained in the spi commands during when clr is or has been asserted. these channels do not recognize code-change commands until a subse - quent cs high condition is recognized, if the removal of the clear condition is observed at least t clrcs prior to the falling edge of cs . in reset mode, the dac code memories are reset to a zero code state and remain in that state until programmed by a subsequent command. applications information thermal design to reduce thermal resistance, include v dd and ground planes in the application pcb. connect the tqfn exposed pad to the ground plane through a large via. connect the multiple v dd inputs to the v dd plane through multiple vias and bypass each v dd pin with a separate 0.1 f f capacitor as close as possible to the supply pin. connect agnd and dgnd to the ground plane. noise immunity each v dd pin should be bypassed with a separate 0.1 f f capacitor as close as possible to the supply pin. pay particular attention to the esr value of the capacitors and add a 100pf capacitor in parallel to each 100nf capacitor. noise is particularly important in fiber applica - tions; thus, it may be necessary to add 100pf capaci - tors to decouple the optional electrodes to ground. this ensures that any crosstalk between the interface and the dac outputs caused by pcb parasitic is minimized. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 36 wlp w363a3+1 21-0024 refer to application note 1891 32 tqfn-ep t3255+4 21-0140 90-0012 downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 27 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. 9-channel, 14-bit current dac with spi interface max5113 revision history revision number revision date description pages changed 0 7/12 initial release ? 1 9/12 released the wlp package and revised the electrical characteristics , table 1, and the 01h?09h: individual dac (1 to 9) configuration registers table. 1, 2, 17, 21 2 5/13 updated note 3 in the electrical characteristics and revised the dac outputs section. 6, 17 downloaded from: http:///

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